Photolithography is a basic technique for forming patterns in semiconductor manufacturing processes. Photolithography generally involves: (1) coating a wafer with a photoresist material; (2) placing a mask having desired patterns (e.g., transparent pattern areas) above the wafer; and (3) exposing the mask and wafer to light. Light exposure causes a chemical reaction in the photoresist which enables the transfer (or printing) of the mask patterns. The wafer is then subject to a development process to remove portions of the photoresist while retaining the desired printed patterns. There are generally two types of photoresists: positive photoresist and negative photoresist. When a positive photoresist is used, the portions exposed to light are removed during development. When a negative photoresist is used, the portions unexposed to light are removed during development. For ease of explanation, throughout this application, various exemplary implementations are described as using the negative photoresist. One skilled in the art will readily recognize that the positive photoresist may be used instead in accordance with any specific design choices.
In semiconductor manufacturing, device miniaturization has been one of the most important research and development goals. One way to achieve this goal is to print (and develop) smaller features (e.g., contact holes) and/or place features closer to each other in the semiconductor devices, for example, by using masks having smaller pattern dimensions or closer-placed patterns. However, as a result of optical diffraction and/or other manufacturing effects, the printed image worsens as pattern dimensions or spacing become smaller. That is, as pattern dimensions or spacing shrink, light passing through the transparent areas on the mask may expose unintended areas around the transparent areas. The exposure of unintended areas causes a reduction in light contrast and results in degraded pattern resolution. Moreover, as the feature size of decreases, distortion in the pattern transfer process becomes more severe as a result of optical diffraction and other manufacturing effects. FIG. 1 illustrates an exemplary image (right figure) printed using the rectangular mask pattern shown on the left. In addition to optical diffraction, distortion and/or resolution losses may be (alternatively or in combination) caused by other non-optical manufacturing effects (e.g., chemical reaction effect, etching effect, etc.).
For ease of explanation, exemplary embodiments to be described herein may from time to time refer to distortions caused by an optical effect. However, one skilled in the art will recognize that other manufacturing effects (whether optical or non-optical) may, alternatively or in combination, cause the distortions to be corrected by the described exemplary embodiments and equivalent processes thereof.
In addition to distortions at the edges of the mask pattern for each feature, a printed image of a feature may also be distorted by optical diffraction from printing its neighboring features. This type of distortion may be explained with reference to FIG. 2. FIG. 2 illustrates an exemplary layout of features (e.g., polygons) on a circuit (e.g., a cell). In FIG. 2, the circuit includes three features (i.e., A, B, and C). As a result of their close proximity to each other, optical diffraction resulting from printing any one feature may cause a distortion in its neighboring features that are being printed at the same time.
The dotted lines in FIG. 2 surrounding each feature indicate an interactive range (or so-called ambit or halo) around each feature. The interactive range of a feature indicates an area from the edges of that feature within which a nearby feature is likely to significantly affect the printing of that feature. In general, the size of the interactive range may be selected based on the physics of the photolithography process (e.g., the size of the lens, the wavelength of light being used, type of resist materials, baking time, baking/annealing temperature, etc.).
FIG. 2 may alternatively be described as illustrating an exemplary layout of a device comprising multiple cells A, B, and C. An integrated circuit device typically comprises numerous cells. Each cell includes multiple layers of features (e.g., a polysilicon layer, a diffusion layer, a metal layer, a contact layer, etc.). In FIG. 2, the device includes three cells (i.e., A, B, and C). In this example, the dotted lines in FIG. 2 surrounding each cell indicate an interactive range (or so-called ambit or halo) around each cell. Like an interactive range around a feature, the size of the interactive range around each cell may be selected based on the physics of the photolithography process (e.g., the size of the lens, the wavelength of light being used, type of resist materials, baking time, baking/annealing temperature, etc.). For ease of explanation, distortions caused by printing a feature, printing neighboring features of a cell, and printing neighboring cells will be collectively referred to as proximity effects.
One technique to compensate for distortions (e.g., proximity effects) caused by manufacturing effect(s) is to use a so-called OPC (Optical Proximity Correction) process. For example, a layout OPC process may be performed on each feature within an integrated circuit layout to make appropriate mask modifications to compensate for proximity effects. Other mask correction processes (e.g., phase shift masks (PSM), scattering bars (SB), chromeless phase masks (CPM), layout modification through compaction, etc.) may be implemented depending on design choice. FIG. 3 illustrates an exemplary OPC process performed on a single layer of a cell (which may contain multiple features) to compensate for proximity effects.
In FIG. 3, a mask pattern is first divided into segments then evaluation points are placed on the segments. A simulation of a photolithographic process using the mask pattern is performed to determine any mismatches (i.e., as a result of proximity effects) at any of the evaluation points. The mismatches are determined by comparing the printed image to an intended image (or the so-called design intent). In FIG. 3, the dotted lines in the lower left figure indicate the printed image and the rectangles around some of the evaluation points indicate mismatches at those points. The mask pattern is modified to compensate (e.g., correct) for the mismatches so that the actual printed image will look more like the intended image. In the example shown in FIG. 3, the edges with the mismatches are moved outwardly by a calculated amount to compensate for the mismatches. The lower right figure in FIG. 3 illustrates the simulated image (see the dotted lines) printed using the modified mask pattern.
An OPC process typically includes an implicit validation process. Alternatively or in combination, a separate validation process may be performed after the OPC process. FIG. 4 will be referred to for explaining both the implicit and separate validation processes.
FIG. 4 illustrates an exemplary validation process that uses control points placed at various locations of a modified mask pattern to determine the processing quality of the previous modification process (e.g., an OPC process). The control points can be any points on a layout and are typically selected along the feature edges where the processing quality (e.g., mismatch, image slope, contrast, defocus latitude, etc.) can be measured. Next, a simulation of the photolithographic process using the modified mask pattern is performed to determine the printed pattern. If an OPC process is performed successfully, the OPC modified mask pattern should pass (as opposed to fail) the validation process with no mismatches outside the tolerances for that feature at any of the control points. Typically, after a successful OPC process, there will still be some small mismatches at some of the evaluation points. These small mismatches are generally within pre-specified tolerances for the pattern and can be referred to as residual errors.
The OPC process sometimes includes an implicit validation process, during which control points are chosen to be the same as the evaluation points. After mask pattern modifications, an implicit validation process can be performed at the evaluation points to determine whether remaining errors are within tolerance. If errors are not within tolerance, additional mask pattern modifications may be performed (e.g., by reverting back to the mask modification step in an OPC process) and another validation process is repeated until all mismatches are within pre-specified tolerances.
The above exemplary OPC process compensates for proximity effects within a cell. However, in practice, a mask correction process (e.g., an OPC process) has to account for proximity effects within a cell and proximity effects caused by printing of neighboring features of other cells. In a typical integrated circuit layout, a cell may appear multiple times at different locations. Each appearance of a cell in a layout may be referred to as a placement of the cell. Thus, a cell appearing at different locations may have different neighboring features. The different neighboring features may cause different amounts of proximity effects to the features of the cell. Consequently, the post-OPC layout typically has multiple copies of the same cell which contain different OPC results (for each type of placement). This process is very computationally intensive and can generate a huge volume of data.
Thus, a market exists for systems and processes to improve mask correction processes (e.g., the OPC process) which may reduce repeated corrections of the mask pattern for the same cell.